IMO the the success of CPU lines in recent years had almost nothing to do the intrinsic properties of the instructions set.
I don't blame MIPs from doing delayed branching etc because if most machine code is compiled from something else, and if most compilers use decent abstractions, one should be changing ISAs all the time to adapt and bolster the latest and greatest implementation techniques. (e.g. for out-of-order super scalar, its probably best to give the CPU some sort of dependency graph.)
The focus on hand-coding as a way to get to know the architecture, on the other hand, borderline insinuates that instructions sets should optimize for hand-coding, which is just plainly ridiculous.
On the other hand, no one wants to have to recompile everything all the time, which gives much force to the argument that CPUs should be more CISC, so that the same (complex) instructions will simply run faster due to hardware improvements. REP MOVS on x86 is a great example of this; it was originally the fastest way to do a block copy until around the Pentium when it lost (only slightly) to very large custom unrolled loops, but since ~P6 it has been internally optimised to copy whole cache lines at once and in the very latest microarchitectures it is once again the fastest.
Well, as a NixOS User (which granted way post-dates RISC), I get the all the benefits of constant recompilation without burning any of my own CPU cycles.
Very good point on the `REP MOVS` front (and cool story!). Indeed if the Mill pans out it would instantly usher the renaissance for branch delay.
So yeah, I rather recompile than try to predict future architecture trends, but either way, the grossness should be there for performance not hand-coding ease.
I don't blame MIPs from doing delayed branching etc because if most machine code is compiled from something else, and if most compilers use decent abstractions, one should be changing ISAs all the time to adapt and bolster the latest and greatest implementation techniques. (e.g. for out-of-order super scalar, its probably best to give the CPU some sort of dependency graph.)
The focus on hand-coding as a way to get to know the architecture, on the other hand, borderline insinuates that instructions sets should optimize for hand-coding, which is just plainly ridiculous.