Why not target verilog directly? Chisel is just a verilog generator in the end. | Hacker News

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hobo_mark on June 13, 2017 | parent | context | favorite | on: Program FPGAs with Go

Why not target verilog directly? Chisel is just a verilog generator in the end.

vasilia on June 13, 2017 [–]

Because of ML and neural networks hype. No one wants to learn VDHL or Verilog, they want OpenCL or something similar.

alunaryak on June 14, 2017 | [–]

I hear what you're saying, but Chisel is a lot closer to an RTL like Verilog than it is to OpenCL.

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